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ECE 2029 INTRODUCTION TO DIGITAL CIRCUIT DESIGN
Lab 2: Introduction to Xilinx Vivado Design Environment
Sign-Off Sheet
Date:
Student 1: __________________________________
Student 2: __________________________________
YOU ARE RESPONSIBLE TO COMPLETE ALL THE ASSIGNMENTS IN THE CHECK LIST BELOW IN ORDER TO
GET FULL CREDIT
Check List
Assignments TA Sign-off
Pre-Lab (MUST be completed before the start of the lab)
Download Vivado on your machine
Watch the tutorial: https://youtu.be/tOwMmBI_XNo
Create a project
Design Entry & Synthesis
Lab part
Create and add a constraint file
Synthesis & Simulation for Timing Verification
Implementation and Downloading
Programming the serial flash.
Submission Details: (Each student should submit files individually on Canvas)
Project File(s) Upload on CANVAS
1. Upload Sign-off Sheet
2. Upload your project files (zip the folder)
Name your file as: lastname_labn_D’20
3. Present your work
Record a 2-3 minute video showing that all parts of your lab functioned properly.
OR
Show your work to TAs for the sign-off.
4. Upload the Writing Assignment (Debugging and Troubleshooting errors FAQ’s) –
OPTIONAL
Due Date: 04/22/2020
Pre-Lab
Usually, laboratory exercises will have pre-lab assignments which are to be completed before
your lab session and must be signed-off by the TA during your lab session.
Pre-labs help you to become oriented to the problem before you enter lab, help complete
your design in advance and prevent wasting time in lab. This second lab is a straightforward
tutorial and does not have a pre-lab.
To complete this pre-lab, you will need to install the Vivado on your machine,
the link to download the software is: https://www.xilinx.com/support/download.html
Assignment
In this second lab you will start by implementing the basic logic gates AND, OR, NOT and the
compound exclusive OR gate (XOR) and verify their truth tables. Then you will implement a multigate circuit. You will do this using the Verilog hardware description language.
1. Start Vivado Design Suite by clicking on Vivado icon and then selecting Create New Project
from the menu. And click next to move to next step.
2. Enter a project name. You should use your network drive as
the project location for your files. Make sure there are no
spaces or special characters (- and _ are allowed) in the folder
name that you create for your work. If you must create you
project on the local disk be sure to back it up to your network
drive when you’re done at the end of lab. Lab machines can be
re-imaged at any time and you could lose your work if it is not on your network drive! Each
partner should have a copy of all the work!
Click Next and then select the RTL project type. Be sure to check the “Do not specify sources at this
time” box and click Next:
IMPORTANT: Watch the tutorial before you begin…
https://youtu.be/tOwMmBI_XNo 25:12 min
Click next and select the correct
Xilinx Artix 7 FPGA that is on the
Basys3 board (XC7A35T1CPG236C)
Click Next, and then Finish on
the New Project Summary
Page. The Project Window
opens:
Design Entry
1. Under the Project Manager, select Add Sources to begin designing your new project.
2. Select Next and then select Create File (click on the + symbol) and enter the file
name for the circuit.
3. Then click OK and Finish. We can now specify the inputs and outputs to create
our AND, OR, NOT and XOR gates. We will use three slide switches as inputs and 4
LEDs on the Basys3 board to display the outputs of each
gate. Inputs A and B will be the inputs to the AND, OR and
XOR gates, and C will be the input to the NOT gate.
4. Click OK. Back in the Project Manager Sources
window double-click the new and_or_not_xor.v file and
you will then see the Verilog file appear in the window on
the right. Add your name and a description of this file to the header description. You
should ALWAYS complete the comment block at the top of each Verilog module that
you write. This is basic professionalism.
5. We can now add the Verilog
statements to design our gates. Enter the
code to your and_or_not_xor.v file as
shown in the figure on the right.
6. Now we can synthesize the design. Click
Run Synthesis in the Project Manager
window. After synthesis is complete there
should be no errors or warnings reported. If
you open the synthesized design you can
see a device level representation (this is
mostly empty since we just have a very
simple design that only uses a tiny, tiny
fraction of the available FPGA resources).
7. Now we can synthesize the design. Click Run Synthesis in the
Project Manager window. After synthesis is complete there should
be no errors or warnings reported. If you open the synthesized
design you can see a device level representation (this is mostly
empty since we just have a very simple design that only uses a tiny,
tiny fraction of the available FPGA resources).
8. You can also look at a schematic representation to see the
input and output buffers and the Look Up Tables (LUT) used. LUTs
can be used to implement any truth table with a certain number of
inputs. Notice that since AND, OR and XOR all have A and B as inputs
they are implemented in the same LUT.
Complete rest of the code
for OR, XOR, & NOT Gates.
9. Save your file, you will continue working from here in the lab.
See you in the Lab…